Altera and Xilinx CPU Core Announcements


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Newsgroups: comp.arch.fpga
Subject: Altera and Xilinx processor core announcements
Date: Tue, 4 Jul 2000 08:40:43 -0700

Altera announced "three families-the Nios soft core embedded processor, the
ARM-based hard core embedded processor, and the MIPS-based hard core
embedded processor" [1]. Also, Altera announced that Motorola and Altera
"have entered discussions toward a licensing agreement to embed Motorola
processor core technology into Altera programmable logic devices" [2].

Xilinx announced "The Xilinx and ARC Cores Alliance for Configurable
Processor Cores on Xilinx FPGAs" [3].

In my Circuit Cellar article series [4-6] I wrote "...this series
demonstrates that a streamlined and thrifty CPU design, optimized for FPGAs,
can achieve a cost-effective integrated computer system, even for low-volume
products that can't justify an ASIC run."

If you will pardon the cliche, these announcements from Altera and Xilinx
have legitimized FPGA CPU soft cores and SoCs.  You will know that FPGA
processor cores are mainstream when we start to see FPGA CPU articles and
performance/size/power tables in Microprocessor Report. :-)

For starters, here's an apples-to-oranges size comparison.  While these
processor cores have quite different features, capabilities, and
performance, all are pipelined RISC embedded processor cores that can run
integer C code.  (A logic cell is a vague unit of FPGA area comprising
approximately one 4-LUT and one FF).

* Nios (16-bit data): 1100 APEX LEs => approx 1100 logic cells
* Nios (32-bit data): 1700 APEX LEs => approx 1700 logic cells
* ARC ("basecase"): 1517 Virtex slices => approx 3000 logic cells
* our xr16 (16-bit data): 130 XC4000x CLBs: (258 4-LUTs, 52 3-LUTs, 165 FFs,
112 TBUFs) => approx 310-420 logic cells
* our xr32 (32-bit data, work in progress) => approx 470-600 logic cells

Jan Gray
Gray Research LLC


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Last updated: Feb 03 2001