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Subject: Xilinx future features?
Date: 24 May 1997 00:00:00 GMT
Newsgroups: comp.arch.fpga

Over on the Xilinx home page there is a very interesting
NetPresentation(tm) by Wim Roelandts, the Pres. and CEO of Xilinx, on the
future of FPGAs -- or more precisely the continuing evolution of the 4K
family.  Much of the talk discusses the transition to 0.25 micron and
smaller processes and the ramifications for mixed voltage systems, speed,
cost, etc.  Quite interesting.

The really tantalizing content occurs about ten minutes into the talk,
where a slide lists some of the new architectural features on the way. 
Here are some highlights:

	32,000 logic cells (400K gates)
	fast re-configure
	hierarchical memory solution

	65,000 logic cells (800K gates)
	build-in logic analyzer
	D/A & A/D support
	custom cores
	high speed differential interface (500 MHz) 

What does this portend?

32K cells, 64K cells -- whew, I still find 800 4-LUT 4010Es pretty roomy.

Fast reconfiguration (partial reconfiguration too, I hope): great.  The 4K
family is not strong in this area.  It would be even better if it shared
some of the XC6200's penchant for direct memory mapped access to internal
device registers and/or SRAMs.

"Hierarchical memory solution" -- perhaps *both* fine grained distributed
select-RAM *and* larger shared blocks of RAM a la the Altera 10K EABs.  Or
even a three-level hierarchy -- for example, 16-bits per logic block
(select RAM), plus 4x256x8 SRAM per 16x16 region, plus one central 16x4Kx8

"Built-in logic analyzer" -- hey, Xilinx is already unique in their device
readback capability.  (Which makes a pretty darn good poor man's simulator,
by the way.)  I suppose they'll add a way to shift out or read out selected
registers and RAM contents, and perhaps 4-LUT outputs, instead of the
current 4K behaviour of dumping everything including the configuration

D/A & A/D support -- high integration to capture more of those DSP design
wins of course.

custom cores -- one can hope for a dedicated PCI or even AGP interface

high speed differential interface -- RMBS?  Even if not, fast inter-chip
interconnect could make it much easier to partion large designs across
arrays of FPGAs and reduce the pressure to go to higher and higher pin

This is going to be fun.

Jan Gray

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