FPGA CPU News of February 2002


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Thursday, February 28, 2002
Anthony Cataldo, EE Times: Researchers challenge conventional FPGA approaches. Report on the FPGA2002 conference this week in Monterey. Many interesting themes, some of which we have touched on here before.

Glitching power

"... actual power consumption within the configurable logic blocks (CLBs) can change wildly depending on the switching activity. This can occur frequently in synchronous circuits, where the inputs to the LUTs come in at different times during the same clock cycle. This "glitching" effect could contribute up to 70 percent of the power dissipation in a CMOS circuit, whether it's an ASIC or FPGA."
From my comp.arch.fpga posting on glitching and clocking:
"Consider one gate G in the middle of an unbalanced, deep, purely combinational logic expression graph. If G's inputs arrive at, and settle at, different times, it may GLITCH high then low then high again, over and over, charging and discharging its output net, and perhaps causing the downstream gates on that net to themselves glitch high and low, and so forth. Result: arbitrary amounts of wasted power due to glitching."

"Now consider the same gate G, but this time in the midst of a pipelined design, with pipeline registers at each two levels of logic. Here, even if G's inputs are unbalanced (perhaps one input sources a gate that sources some registers, another input sources another register directly) then there will be at most one glitch originating at G, and since its output is registered, this glitch is not seen by downstream gates. Result: less or no power wasted due to glitching."

"Some are faster than others"

"Routing structures is another area that is subject to constant scrutiny. ... For its Dali core, ... Altera chose a heterogeneous set of wires that are functionally identical but some are faster than others."

'"You can remove 30 percent of the critical path delay if you speed up 20 percent of the global interconnect wires," said Altera's Michael Hutton. "After that it's diminishing returns."'

Last summer I wrote (subtopic "Power"):
"Similarly, it seems to me that power reduction can be and must be targeted in the FPGA VLSI implementation, in the FPGA architecture, in the P&R tools, in the synthesis tools, and in the design methodology."

"(For example, perhaps some programmable interconnect could be speed optimized, and other routing, power optimized. The (timing driving) P&R tools know which nets are time critical and could put those on the speed optimized routing channels -- and conversely move slack time nets to lower power (smaller drivers/no drivers) channels.)"

Thursday, February 14, 2002
Today I've been writing some Verilog targeting Virtex-II. V2 is so fast that I'm going to have to unlearn some things. For instance, prior to V2, I would usually have to replicate the FFs that drove high fanout ALU control signals to cut down on net loading and delay. In Virtex-II, I have a simple FF driving a control signal with 32 loads and the worst-cast delay is under 1 ns. (Just like Xilinx said it would be.)

Here's a nice short article from an April 1998 UK Electronics Weekly article on the history of ARM. Steve Furber:

"The general view was that microprocessors had a mystique - that they were designed by very special people. ..."

"Sophie [Wilson] and I went on a trip to Phoenix to the Western Design Centre which was working on a 16-bit version of the 6502. We found it to be a cottage industry working in a bungalow in a back street. That gave us confidence," recalls Furber, "Sophie started playing with instruction set design. Our mentality was let's have a go at building a microprocessor." The next problem was to persuade the boss."

"... Building our own microprocessor was a crazy idea - but he backed it."

Hermann Hauser:
"... but when we decided to do a microprocessor on our own, I made two great decisions - I gave them two things which National, Intel and Motorola had never given their design teams: the first was no money; the second was no people. The only way they could do it was to keep it really simple."
Simple is beautiful.

Monday, February 11, 2002
Altera introduces Stratix, its "killer" new FPGA architecture. Data sheet. Stratix looks great. Huge. Fast (the RAM is anyway). I love the three tier RAM hierarchy. I still prefer XC4000/Virtex/Virtex-II architectures but perhaps the time has finally come to design that two-vendor-optimized FPGA CPU core.

(There's also a web cast that I haven't watched yet.)

Over time, the major architectural differences between Xilinx and Altera are fading. It seems to me that Altera's architecture is slowly evolving towards the uniform sea of CLBs (OK, LABs), with lots of local interconnect, that Xilinx has provided from day one. As I wrote last year when Mercury debuted,

"As proposed FPGA architectures are increasingly validated and tuned by recompiling existing customer designs against them, perhaps over time all of the various FPGA architectures will evolve into the same basic topology, varying only on the way the hierarchies of local, intermediate, and global interconnect are "chunked". So for example, we'll have Virtex-II with 8 LUTs per CLB competing with 10K/20K/Mercury at 10 LEs per LAB. And now we'll have a more "local" extra-LAB interconnect in Mercury."

Anthony Cataldo, EE Times: Altera courts ASIC designers with block-based Stratix PLD.

"Perhaps more important, the interconnect is uniform across the die, and with the help of Altera's latest tools designers can freeze functional blocks and reposition them on the design or use them for another design without having to resynthesize."

Crista Souza, EBN: Altera looks to regain PLD crown with Stratix.

"Fundamental to Stratix is a block-based methodology that lets multiple engineers work in parallel on different parts of the same system design. The timing characteristics of each block can be locked in before layout to guarantee performance and functionality when the blocks interact with each other, according to Altera."
That is where Xilinx has always shone in the past.

Mark Long, e-inSITE: Altera Unveils New PLD Device Family.

Ray Andraka's comments.

Austin Lesea, Xilinx, comments (comp.arch.fpga): "Imitation is the sincerest form of flattery."

While my opinion is that Xilinx has been the greater innovator in the programmable logic industry, it is clear that both Altera and Xilinx have adopted device features that first debuted in their competitor's products.

In any event, this hyper-competition is good for customers and, ironically, good for the PLD vendor. As they race to field "killer" products, introducing killer new features such as embedded dual ported block RAM, programmable DLLs, digitally controlled impedance, and high speed serial links, they end up killing, not each other, but rather other implementation technologies that have the thankless task of holding their ground against increasingly fast, dense, cheap, and capable FPGAs.

To recycle Eugene Brooks' famous catch phrase,

"There is no defense against the ATTACK OF THE KILLER FPGAS!"

Saturday, February 2, 2002
OT: Nixie Clock Gallery.

Friday, February 1, 2002
Tim Böscke: Minimal 8 Bit VHDL CPU designed for a 32 macrocell CPLD. One page of VHDL!

FPGA CPU News, Vol. 3, No. 2
Back issues: Vol.3 (2002): Jan; Vol. 2 (2001): Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec; Vol. 1 (2000): Apr Aug Sep Oct Nov Dec.
Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.

Copyright © 2000-2002, Gray Research LLC. All rights reserved.
Last updated: Mar 02 2002