FPGA CPU News of August 2000


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Wednesday, August 30, 2000
Each year I try to attend Hot Chips, and sometimes, Hot Interconnects, to listen and learn. Stanford is lovely in August. This year I couldn't make it. But my trip to the Hot Chips web site was rewarding. They have posted the presentation slides, in PDF, for 'Chips VIII (1996) through 11 (1999). Thank you, Hot Chips organizers and volunteers.

Tuesday, August 29, 2000
FPSLIC ships
Atmel: Atmel Ships Industry's First RISC-based Programmable System-on-a-Chip called AT94K. It's an 8-bit AVR CPU, 30 MIPS at 40 MHz, 2 UARTs, timer/counters, interrupt controller, programmable I/O, 36 KB of SRAM, and an embedded AT40K FPGA with up to 50,000 programmable logic "gates".
"... Unless a company will ship millions of systems utilizing the custom system-on-chip, it is hard to justify the cost, risk and time-to-market issues associated with custom SOC development today. ... Now every designer can benefit from the combination of system-level integration and programmability in a single device -- at a price level that supports volume production..."
Strangely enough, there is no flash ROM, despite Atmel's leadership in flash memory and the unique integration advantages embedded flash could give Atmel compared to Triscend, Altera, and Xilinx SoCs.

Tom Cantrell, Circuit Cellar Online: Atmel Gets Huge.

It's "priced from $50". Compare that to the current price of an XC2S50-5TQ144, <$15 Q1, which can implement a >50 MHz 16- or 32-bit RISC processor and integrated SoC, with several tens of thousands of FPGA "gates" free. Of course, then you'll need an external SRAM. Presumably the FPSLIC would be a lower power solution.

first fibs
Speaking of firsts, Altera's excellent Excalibur backgrounder describes their Excalibur processor solutions as "the first RISC processors to be optimized specifically for programmable logic" and asserts "As the first RISC processor soft core to be developed specifically for programmable logic, Nios ...".

This questionable temporal one-upsmanship denies the innovation, not to mention the existence, of numerous FPGA RISC processors and processor cores, including Philip Freidin's 1991 RISC4005/R16, the 1995 j32, whose source code was available (briefly) on the web early in 1996, XSOC/xr16 (published in Circuit Cellar, source code here, months ahead of the Nios announcement), and even numerous universities that have been building RISC processors in FPGAs for years.

"It is amazing what you can squeeze onto these parts if you design the machine architecture carefully to exploit FPGA resources." -- Homebuilt processors (1994)
"The xr16 design is optimized for an area-efficient pipelined implementation in a field-programmable gate array and other gate- and interconnect-constrained environments. -- The xr16 Specifications, p.1 (part of the XSOC Kit)

Monday, August 28, 2000
FPGA datapaths from software inner loops
Richard Goering, EE Times: Compiler project marks Synopsys' step into post-ASIC world. "The compiler takes in pure ANSI C code and automatically selects computationally intensive loops that can be greatly accelerated in hardware. The code is turned into data-flow graphs and compiled into the data path, which in the research prototype is represented by a Xilinx Virtex FPGA, although researchers expect that other reconfigurable data path arrays will offer better cost and performance in the future."
'But will dynamically reconfigurable SoC architectures replace ASICs for some of those applications? "They will have to," Harr said. "More and more standards are designed for lots of variance. ASICs won't win in the long run when set-top boxes have to support 20 different formats."'
Instead of the MicroSparc-II, perhaps they should consider using one or more compact, fast FPGA CPU cores in the Virtex-1000 itself. See Inner loop datapaths and Soft cores.

32-bit configurable SoC
Craig Matsumoto, EE Times: Triscend adds 32-bit configurable SoC line. "... while the E5 was based on an 8-bit 8032 microprocessor core, the A7 is based on the 32-bit ARM7 developed by ARM Ltd."

Like programmable logic vendors, Triscend is benefiting from increases in ASIC mask costs. One of the company's telecom customers reports paying $500,000 for 0.15-micron mask sets, and one customer in the computer industry has reported mask costs of $1 million for a 0.13-micron part. "It's doubling every process generation, based on what we've heard," Chaffin said.
'"If you take an FPGA and try to put it on a bus, you have to develop a lot of interconnect circuitry," he said.' Yes, but if you unite an FPGA CPU core with a on-chip bus controller core and a glueless peripheral core architecture designed for reuse (XSOC), you don't, and you get to ride the commodity bulk programmable logic price reduction curve too. On the other hand, you might miss out on some splendid hardware integration and embedded development support features.

new FPGA partitioning tool
Richard Goering, EE Times: Startup SpeedGate promised better FPGA partitioning. "Faced with approaches that are too granular and not granular enough, SpeedGate believes it has found the approach that is "just right." FPGA Stuffer partitions at the process level. That's one step down from the module level, since modules are collections of processes and instantiations of other modules. In Verilog, an "always" block or a continuous-assignment statement typically denotes a process."

Xilinx: Xilinx and Michigan State Launch First Web Site To Support University Engineering Programs. Visit the Xilinx University Resource Center!

Xilinx: IBIS backgrounder (PDF). "IBIS models consist of look-up tables that predict the I/V characteristics and dV/dt of integrated circuit inputs and outputs when combined with the PCB wiring."

Wednesday, August 23, 2000
Murray Disman, ChipCenter: Kentron's Quad Band Memory. Remember interleaved DRAM memory banks? Designers achieved higher bandwith by ganging multiple memory banks and cycling their output enables. (Those days ended when EDO DRAMs and then SDRAMs replaced FPM DRAMs.) QBM reportedly uses FET switches to achieve a simliar effect with DDR SDRAM modules.

Tuesday, August 22, 2000
Xilinx: Software Dominance. See especially "High Level Languages improve Time to Market; System-C / Java Adoption begun" including "synthesis vendor partnership" and a "System C / Java Compiler". A very interesting development. Xilinx seems to be investing to make FPGA design accessible to software engineers. Learn more: SystemC, LavaLogic.

Monday, August 21, 2000
Altera and Xilinx have announced that they will build FPGAs with hard processor cores. Triscend and Atmel already sell similar products. Do hard CPU cores make programmable logic soft cores irrelevant? Soft cores in a hard world.

Saturday, August 19, 2000
I am open sourcing CNets, moving it to sourceforge.net, and I am inviting you to collaborate on its evolution. See cnets.sourceforge.net.

Dave Conroy's PDP-8/X in an XCS10 and an XCS05 IOU. Apropos of netlist generators:

"With the design partitioned into two chips and the structural model done, all I needed to do was transform the logic from the model into a form which could be fed to the XILINX place-and-route software. This was not done by drawing schematics, or by describing the logic in VHDL/VERILOG and feeding it to a logic synthesis tool. Instead, I did it by describing the logic in the form of a C++ program, the output of which was a standard XILINX wirelist (in XNF format), which could be fed to the XILINX place-and-route software."
Right on!

Ray Andraka in EE Times: FPGAs cut power with 'pipeline'. Which reminds me: FPGA synthesis tools lose battle with John Henry. Ray also has some excellent reading at his web site.

Friday, August 18, 2000
Circuit Cellar Online: Excalibur Marks the Spot (PDF). "[RISC4005]...[xr16]... These and other pioneering designs have demonstrated that a soft-core running in an FPGA can achieve a practical level of functionality, performance, and price."

EE Times: Lucent hybrid combines FPGA, ASIC features. "Lucent Technologies Inc.'s Microelectronics Division is prepared to offer chips anywhere in the spectrum between FPGAs and ASICs, a flexibility that company officials say is unique."

Joel on Software: The Joel Test: 12 Steps to Better Code. Good ideas for both software and hardware engineering projects. I used to work where Joel used to work, and through my career I've worked on 4/12 projects and 12/12 projects, and believe me, the 12/12 projects were much more pleasant and produced much better results in less time.

"If you're trying to decide whether to take a programming job, ask your prospective employer how they rate on this test. If it's too low, make sure that you'll have the authority to fix these things. Otherwise you're going to be frustrated and unproductive."

FPL 2000: 10th International Conference on Field Programmable Logic and Applications, Villach, Austria. The program looks very good.

Thursday, August 17, 2000
I just received my copy of MMIXware: A RISC Computer for the Third Millennium by Donald E. Knuth. MMIX replaces MIX as the virtual machine in forthcoming volumes of Knuth's The Art of Computer Programming. Should be lots of fun!

"This book is a collection of programs written in CWEB that make MMIX a virtual reality" including an assembler and two simulators, one which provides superscalar execution with any number and variety of functional units, caching, and branch prediction strategies. I bet it won't be long before some enthusiastic FPGA CPU hacker makes MMIX a real reality.

Veriwell sightings
In the XSOC Getting Started Guide, I lament that I was unable to find a copy of the Veriwell free Verilog simulator on the web now that wellspring.com is no more. Fortunately Arrigo Benedetti found this link (Veriwell 2.1.7). (Of course, Gray Research LLC cannot vouch for the provenance of this software, which may carry viruses, etc., use at your own risk.)

This version seems to run the xsocv/xsoc.prj Verilog XSOC/xr16 testbench in the XSOC project kit. Quoting from its README.1ST:

Copy Policy
SynaptiCAD encourages the unlimited copying of VeriWell! VeriWell is copyrighted, yet freely distributable. Unlike most other software that is protected by a hardware key, VeriWell WILL run without one. We want to make Verilog HDL accessible to anyone who wants to use Verilog for whatever reason -- evaluation, education, training, etc.

The Concept of "Free" and "Registered"
VeriWell runs in one of two modes: "free" and "registered". In the "free" mode, VeriWell enables all features and functions, but limits the size of the input model to a total of approximately 1000 lines. This limit was selected by University Professors and Verilog users. This should give the user enough capacity to run small-to-medium-sized models for coursework, training, evaluation, and even some commercial applications.

Thanks to the authors of this useful software for their beneficence.

Industry news
Xilinx Incorporates Next-Generation Technology into Free WebPACK Software. Free tools for XC9500 and CoolRunner Series CPLDs. Perhaps someone can look into these downloads and let us know whether they are useful for writing and simulating arbitrary Verilog code (even if you don't in the end build a CPLD configuration).

Catching up dept.
June 12, 2000 Altera announces Nios soft cores with GnuPro tools support. Smart. They also announce they have licensed ARM and MIPS hard cores and are in discussions with Motorola. Coverage from me, Murray Disman, EE Times.

July 3, 2000 Xilinx and ARC Cores announce alliance. Disman: "The Xilinx and ARC Cores program is a much more expensive proposition that will be primarily used to prototype ASIC designs". Contrast that to the theme of my Circuit Cellar articles.

July 25, 2000 IBM and Xilinx announce they are working together "to embed PowerPC hard cores" into Virtex-II FPGAs and to license the "CoreConnect bus for integration into Xilinx FPGAs." Disman. The crucial FPGA on-chip bus interface contest is coming into focus.

EE Times: Analysis: FPGAs muscle in on ASICs' embedded turf.

Sunday, August 13, 2000
Now CNets2000 can emit Verilog as well as EDIF: Generating Verilog from CNets2000.

Friday, August 11, 2000
The right tools are important. I want an easy, extensible, free, text-based design representation with the explicit mapping and placement control of schematics: Introducing CNets2000.

Monday, August 7, 2000
I am starting on a major cycle to port xr16 (and the not yet quite finished xr32) to Virtex. I will probably also do a new 32-register machine to make it easier to port GCC, binutils, et al via a cross-assembly or cross-targeting-linker strategy: XSOC2 Agenda.

I expect to see two different configurations of the processor cores: one with a dedicated instruction and/or data block RAM (no external RAM) and one with block RAMs for I-cache or D-cache: XSOC2 and block RAMs.

If you want to be a great Virtex-optimized core designer, you first have to acquire The Virtex Knowledge.

For fun, last night I decided to port xr16 to Virtex to see how fast she'll run "out of the box": First steps.

Friday, August 4, 2000
Does FPGA CPU/SoC design have a place in undergraduate and graduate level computer architecture courses? I think so. See my paper for the Workshop on Computer Architecture Education the 2000 International Symposium on Computer Architecture: Teaching.

FPGA CPU News, Vol. 1, No. 2
Back issues: Apr.
Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.

Copyright © 2000-2002, Gray Research LLC. All rights reserved.
Last updated: Feb 13 2001