FPGA CPU News of May 2002


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Wednesday, May 15, 2002
Naohiko Shimizu, Tokai University, announces his GPL'd m65 FPGA CPU core.
"m65 is provided as a synthesizable soft IP core under GPL. The description language is SFL and can be synthesized for any FPGA such as ALTERA or Xilinx. When synthesized for ALTERA FLEX10K series, it will fit within 600 logic cells. I successfully complied for a FLEX EPF10K10LC84-3."
If I recall correctly, 600 LUTs is the smallest result I've seen for a legacy CISCy 8-bit CPU core. For example, Rob Finch has one that fits in 800 LUTs; and Free-IP's implementation needs over 1000 LUTs. (But who knows how these cores compare on performance?)

Also from this lab: My80.

I downloaded the m65 gzipped archive and skimmed the source code, written in SFL. Interesting. NTT's SFL (Structured Functional description Language) is a synthesis-oriented behavioral HDL for synchronous circuits, apparently with support for explicit tasking and pipelining. (In contrast, Verilog and VHDL were originally simulation-oriented, modeling asynchronous systems; they handle synchronous systems with an idiom (such as always @(posedge clk) etc.). SFL seems to have appeared roughly at the same time as VHDL, but (obviously) did not catch on (relative to the ubiquity of VHDL and Verilog). I wonder why -- it seems a more expressive, appropriate, and effective specification language for pipelined synchronous digital systems. Well, you never can tell -- there are always so many factors that determine winner-take-all technology adoption! (If anyone knows the story of SFL vs. Verilog/VHDL, please let us know.)

To build m65 from SFL, you must convert the SFL to VHDL or Verilog using the PARTHENON tools.

Richard Goering, EE Times (1994): NTT synthesis comes to U.S.:

'However, SFL still permits design entry at a very high level, according to Adams. "There's no information about connections," he noted. "In VHDL, you have to say that signal A will go to signal B. In our system, it's like programming--you just make a call to a function and pass in arguments."'

Tuesday, May 14, 2002
Anders Lindström, Johan E. Thelin, Michael Nordseth, Chalmers University of Technology, The Jam CPU. (Here's another link, I don't know which is the authoritative version.) A classic DLX-based 5-stage pipelined 32-bit RISC in VHDL, licensed under LGPL v2.1.

Accompanied by the Concert'02 Architecture Specification and Implementation, a very nice write up of this work.

24 MHz, ~3100 LUTs in XCV300; 51 MHz, ~3100 LUTs in XC2V3000; 42 MHz and 4789 "ATOMs" in Altera Mercury EP1M350.

Saturday, May 11, 2002
There's yet another FPGA CPU thread on slashdot.org.

Tuesday, May 7, 2002
R. Colin Johnson, EE Times: Souped-up C compiler autoconfigures FPGAs.

Colorado State: Cameron: Compiling high-level programs to FPGA configurations. Publications.

Altera: Altera and TSMC Collaborate on Nexsys Based 90-Nanometer Process Technology for PLDs.

Gale Morrison, Electronic News: Altera Commits to 90nm PLD Production.

"Now, the industry is under incredible financial pressure and is taking steps -- via R&D and foundry alliances -- to group into what looks like perhaps four teams globally."
Altera: Altera Ahead of the Pack with Excalibur Solutions.

Sunday, May 5, 2002
I must have been away from the software world for too long. I haven't needed the word reify for at least a year.

Neat course
Philip Leong, CUHK: CEG5010 Rapid Prototyping of Digital Systems. Custom computing with Pilchard! Prof. Leong's lecture notes are quite interesting.

Prof. Leong is also a co-chair of the first IEEE International Conference on Field-Programmable Technology (FPT), Dec. 16-18, 2002, Chinese University of Hong Kong.

Another non-US FPGA conference of note is the 12th International Conference on Field Programmable Logic and Applications, Sept. 2-4, 2002, Montpellier, France.

Also coming up this month and in June, in various cities, is Insight's free X-FEST'02. It looks good, Virtex-II Pro oriented, and will presumably be more in-depth technical than the recent Programmable World seminars. Unfortunately I won't be able to attend.

Saturday, May 4, 2002
New FPGA processor
Ponderosa Design's scc-II Microsequencer. Coverage in XCell Journal 42 (Spring 2002). (PDF version.) Includes an interesting project that implements a simple ethernet interface requiring only an external PHY.

A first glance, scc-II seems most comparable to PicoBlaze (nee KCPSM) in its aspirations. Yet it is a 16-bit stack machine that is "supported by C-like high-level language". 400-600 LUTs. Up to 70 MHz in Virtex-II.

Wednesday, May 1, 2002
Xilinx announces PicoBlaze: KCPSM rebadged. (And productized? Will it be a supported product some day?)
"Formerly known as KCPSM, the PicoBlaze processor runs at speeds of 116 MHz, yet occupies a tiny footprint of just 154 logic cells."
My sincere congratulations and best wishes to PicoBlaze's creator, Ken Chapman of Xilinx U.K., a true pioneer in this field. It took Xilinx a mere seven years (or so) to come to appreciate the great utility and value of this work, and market it as such. The only thing sweeter would be if Xilinx would recognize, exhume, Virtex-ize, and productize Philip Freidin's seminal 1991 RISC4005 work.

So now we have MicroBlaze (32-bits) and PicoBlaze (8-bits). Some diminuitive SI prefixes: milli, micro, nano, pico.

Joke definition: millihelen: beauty sufficient to launch one ship.

Nios on Stratix
Altera: Nios Soft Core Processor Rides the Performance Curve on Altera's Stratix Device Family. 125 MHz in the not yet shipping Stratix family. Necessarily that implies excellent performance in and around the Stratix embedded RAM blocks, in which Nios implements its SPARC-like windowed register file.

"Since its introduction in 2000, the Nios soft core processor is being used by more than 6,100 engineers around the world."

Anthony Cataldo, EE Times: Altera readies cores, tools for upcoming Stratix.

[updated 05/06/02]:
Another quote from the Altera press release:

"Targeting Stratix devices results in a savings of up to five hundred logic elements (LEs) when compared to other device families."

Mark Long, e-inSITE: New Soft Core Processor Features Stratix Device Support.

MicroBlaze on Virtex-II Pro
Xilinx: Xilinx Widens Undisputed FPGA Processor Leadership. 150 MHz and 100 D-MIPS in Virtex-II Pro. Pretty darn good numbers, likely revealing the V2Pro fabric is about 150/125 => 20% faster than the V2 fabric.

I wonder what these performance numbers fall to, when interfaced to the fastest possible external memory solution, instead of using on-chip RAM. As I discussed on comp.arch.fpga,

  • if you're not going off-chip, a <200 LUT 16-bit (address space) RISC is usually sufficient;
  • these 100+ MHz soft processor cores will need I-caches, at least, for good performance when interfacing to relatively higher latency, lower bandwidth off-chip RAM.
"... 9,480 Xilinx processor users to date ...": I would like to see Xilinx better substantiate this assertion. Does it refer to MicroBlaze and KCPSM design-ins? KCPSM downloads? (I doubt MicroBlaze dev kit sales number one third of nine thousand.) If this figure includes KCPSM downloads, Xilinx could boost the number by a further ~2000 by also counting XSOC/xr16 downloads. :-)

This PR seems like a marketing response to Altera's apparent uptake in Nios kit sales. It wasn't so long ago that Altera's Nios kit numbers were stated in the two thousands area. (At ESC an Altera person told me their Nios user numbers do not double count installations of Nios 1.x and 2.x (which is a common way that software vendors inflate their sales numbers).)

[updated 05/13/02]
Murray Disman, ChipCenter: Xilinx Claims Soft Processor Lead.

"There is, however, an important difference between the two numbers. Altera asserts that all of the 6,100 users bought Nios design kits at a price of $495. The vast majority of the Xilinx users are those that downloaded the PicoBlaze (KCPSM) core for free. The number of MicroBlaze design kits, also priced at $495, shipped by Xilinx is less than 10% of the number of Nios kits shipped by Altera."

Jim Turley, in Circuit Cellar magazine: Design Your Own Microprocessor. Alas no mention of my Circuit Cellar series, this site, nor the fpga-cpu list!

Today, I wish I was at the Embedded Processor Forum, particularly to catch the Proceler talk by Dr. Sudhakar Yalamanchili.

Anthony Cataldo, EE Times: Processor forum examines embedded cache, architectures.

FPGA CPU News, Vol. 3, No. 5
Back issues:
Vol. 3 (2002): Jan Feb Mar Apr;
Vol. 2 (2001): Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec;
Vol. 1 (2000): Apr Aug Sep Oct Nov Dec.

Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.

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Last updated: Aug 13 2002