FPGA CPU News of September 2002


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Monday, September 30, 2002
More Cyclone news
Altera Introduces Industry's Lowest Cost Configuration Device Family.

Altera Extends Embedded Processor Leadership with New Low-Cost Solutions.

Altera Launches Free Embedded Processor Portfolio.

I did a double take when I read "Altera Ships More Than 100 Ready-to-Use Embedded Processor Cores Free of Charge", (my emphasis), but now I take this to mean integrated peripheral cores, not processors.

FPGA IP business model redux
In the short term, all these free cores are great news for the FPGA SoC designer.

However, these same welcome developments may well conspire to make for a challenging market for me-too third-party FPGA soft cores IP vendors, and IP vendors who don't "get with the program" and embrace the coming System Builder IDE products.

Unless FPGA vendors play their cards skillfully, they risk suffocating their nascent third-party FPGA IP ecologies. In the long term, there may be a less healthy, less diverse ecology than had the FPGA vendors not "given away the store".

On the other hand, by making it easy to use/reuse/integrate unique IP, FPGA vendors' System Builder products might arguably grow the reusable IP market, from the current dozens of potential customers, to many thousands of potential customers, by making it fiendishly easy to don the system architect hat -- or so it seems...

This all harkens back to my now-two-year-old essay on FPGA IP business models.

"If FPGA vendors give away enough free cores, the end effect could be to discourage pure IP vendors from contributing to that device vendor's value chain, reducing the supply of device optimized cores, hence design wins, hence device sales."

The Challenge for third-party IP vendors
Who will pay a thousand dollars for a "me-too" third party memory interface core when the FPGA vendor gives one away for free? Particularly when the FPGA vendor's core is wrapped up with a bow, packaged, integrated, and plugged into their "System Builder" integrated development environment? When their core ...

  • Is already there on the modules menu?
  • Is already there in the preinstalled "verified plug-and-play cores catalog" documentation?
  • Is already integrated into the system bus configurator?
  • Is already integrated into the firmware configurator?
  • Is already integrated into the system test bench generator?
  • Is already available for instant download or free-upgrade-to-latest-version
  • from the vendor's site?
  • Is already tried, cursed at, shook out, debugged, fixed, proven, vouched-for,
  • by dozens of other customers?
  • Is already known to correctly interoperate with the other cores in the target system?

(Note, I am not stating that such facilities are provided by any current System Builder IDE product, but it's just a matter of time. "A simple matter of programming." Almost a foregone conclusion.)

Can you say network effects? I knew you could.

What to do?
What should third party IP vendors take away from this development?

  • Because FPGA vendors stand to profit from giving away high quality IP, the rules of the The FPGA IP Game are quite different from The ASIC IP Game;
  • Most "Me-too" IP is worthless;
  • "Me-too" on-chip buses are worthless;
  • "Me-too" design environments are worthless;
  • Your cores must ship, must shine, as plug-ins to System Builder IDEs;
  • FPGA vendors can't do everything well; therefore, there is still opportunity for:
    • special, high-value, domain-specific IP; and
    • vastly superior, highly crafted, higher-speed, LUT-miserly, "me-too" IP;
  • Think system, think platform, (think reference platform), think integrated, think solution, think works right out of the box;

    I believe there are opportunities for third parties to sell preconfigured FPGA SoC reference platforms for specific problem domains. Here the value-add is as likely to be in the software and business domains as in the hardware domain.

    Your customers might be end-user engineers. Or they might be the FPGA vendors themselves, eager to acquire IP that enables them to establish volume design wins in new markets.

I used to think "the two on-chip bus interfaces (to processor, to peripherals) define the platform" -- I was wrong. Repeat after me:

The System Builder is the Platform.
The System Builder is the Platform.
The System Builder is the Platform.

And EDA companies, if you have aspirations to launch a system-designer-canvas-IDE-type product in the FPGA space, you'd better act fast, because it looks like the train is leaving the station.

Climate change and an ecology on the decline
In my earlier comments on Altera's SOPC Builder, I noted how it reminded me of Visual C++ 1.0. How that product changed the subject, from compiler superiority/code quality, to integration/programmer productivity/rapid application development.

Over the years, Visual C++ (and yes, Visual Basic) evolved into the present, sprawling, stunningly all-encompassing, Visual Studio.NET. A magnificent edifice, a cathedral -- no, switch metaphors -- a Las Vegas of development environments, catering to almost every whim and appetite.

This past April, following FCCM'02, I stopped by the spring Software Development Expo, in San Jose, CA.

I remembered the glory days of SD Expo, ten years ago, when Microsoft and Borland were having it out. The palpable excitement, the buzzing bazaar of the exhibitor halls, with hundreds of little companies with various specialty tools. Here a half dozen programmer's editor companies, there a half dozen version control companies, over there several debugger companies, linker vendors, class library vendors, CASE tools vendors, and so forth.

What a difference a decade makes. This year, the exhibit hall seemed maybe a quarter of its old size, and none of its old energy. Maybe this is what the (mythical) COBOL Expo used to look like before they packed it up for good.

What changed? One factor is the poor business climate. Another is on the open source movement, and the rise of pretty damn good free tools. Other factors include the fractured development landscape, the somewhat stagnant PC software market, the developers who moved on to Internet development, or those who moved on to (e.g.) Java development and better targeted Java developer's conferences.

But there's probably another factor. As VC++ evolved and acquired editing, debugging, class libraries, version control, CASE tools, etc., this "platform climate warming" challenged the third-party value-chain/add-in ecology.

Companies that zigged to Microsoft's zag, or companies like Rational, with key complementary "star IP" (if you will), still live and thrive in this ecosystem. But in the context of bundled, well integrated features, "me-too" third-party products will be on the decline.

So the lesson for third-party IP vendors is to zig to the FPGA vendor's zag, and you can do (very) well. (Thanks to Dave Winer for the zig/zag concept.)

The good news
Personally, I find this System Builder IDE development liberating and empowering.

In the past, if you wanted to pursue your specialty, be it specialty interfaces, specialty signal processing, or specialty processor architecture, your (not standalone) part of a larger system-on-a-chip solution was a difficult sell.

To make your core available and usable for evaluation by potential customers, you would have little choice but wrap it up in a reference platform. Maybe you'd have to build or acquire memory and peripheral interface cores. Maybe you'd have to build yourself a reference system PCB.

All that packaging could well be more work (and in the universe of cores' reference design packaging, useless, valueless, redundant work) than went into your specialty core in the first place.

In my company's case, our processor cores were uninteresting absent complementary glueless on-chip buses, glueless peripherals, and absent a reference system PCB.

The coming System Builder era washes away much of that waste. Now a specialty core vendor, provided they go to the effort of packing up their product as a plug-in module, can be spared much of that zero-value reference system packaging effort.

Takeaways for System Builder designers

  • Take care of your nascent ecology;
  • Go out of your way to help third parties integrate their wares into your IDEs. Strive to keep a level playing field -- in particular, expose and document software and hardware integration interfaces, and maybe even share market research -- such that a third party plug-in has the same opportunities for integration, polish, and customer-interaction as your in-house modules;
  • If a partner is serving a niche well, think twice before giving away an equivalent product...

Wednesday, September 25, 2002
On Oct. 2, 2002, Peter Ryser of Xilinx will speak to the Silicon Valley Linux User's Group, topic Linux on Programmable Hardware.
"As part of his talk, Peter will explain how the hardware inside the FPGA device can be upgraded even after deployment and how hardware functionality, similar to the Linux kernel modules, can be loaded or replaced at system run-time."

Monday, September 23, 2002
Altera Cyclone
Another nail in the ASIC coffin.

Altera: Altera's Cyclone FPGAs Take the Industry by Storm. Data sheet (PDF). Backgrounder (PDF). Q&A. Quotes.

Anthony Cataldo, EE Times: Altera spins Cyclone, stripped-down FPGA.
Crista Souza, EBN: Altera's Cyclone helps level FPGA costs.
Mark Long, e-inSITE: Programmable Logic At ASIC Prices?.
Alex Romanelli, Electronic News Online: Altera Pits FPGAs Against ASICs.
Reuters: Altera Unveils New Programmable Chips.
Xilinx: Xilinx Ships 40 Millionth Spartan Device....
[updated 10/06/02] Murray Disman, ChipCenter: Altera's Low Cost FPGAs.

Let's compare.

         BRAM         02  03  04         03
Device     Kb  KLUT  BAP BAP BAP Ref $/KLUT
XCS05XL     0   0.2 $2.55        [3] $12.75
XC2S50E    32   1.5   $7         [2]  $4.67
EP1C3      52     3       $7  $4 [1]  $2.33
EP1C6      80     6      $17  $9 [1]  $2.83
XC2S300E   64     6  $18         [2]  $3.00
EP1C12    208    12      $35 $25 [1]  $2.92
EP1C20    256    20      $60 $40 [1]  $3.00

XC2V1000  640    10
EP1S10    752    11
EP1S20   1352    18
XC2V2000  896    22

BRAM Kb: Kbits of block RAM
         (excludes parity bits, LUT RAM, and "M512s")
KLUTs:   thousands of LUTs
BAP:     best announced price, any volume
$/KLUT:  approximate 2003 BAP/KLUTs

[1] Altera Cyclone Q&A: "High-volume pricing (250,000 units) in 2004 for the EP1C3, EP1C6, EP1C12, and EP1C20 devices in the smallest package and slowest speed grade will start at $4, $8.95, $25, and $40, respectively. ... Pricing for 50,000 units in mid-2003 for the EP1C3, EP1C6, EP1C12, and EP1C20 devices in the smallest package and slowest speed grade will start at $7, $17, $35, and $60, respectively."

[2] Xilinx Spartan-IIE press release: "Second half 2002 pricing ranges from $6.95 for the XC2S50E- TQ144 (50,000 system gates) to $17.95 for the XC2S300E-PQ208 (300,000 system gates) in volumes greater than 250,000 units."

[3] Xilinx Spartan prelease: "Spartan pricing ranges from $2.55 for the XCSO5XL-VQ100 (5,000 system gates) to $17.95 for the XC2S300E-PQ208 (300,000 system gates) in volumes greater than 250,000 units."

Comments: Comparing press-release 2002, 2003, and 2004 volume prices is meaningless -- worse than comparing apples to oranges. Nevertheless, the obvious price trend for next year is towards $3/KLUT, and the XC2S300E is "already" there. The year after that, prices approach $2/KLUT.

The price breakthrough is at the low-end -- the (2004) $4 EP1C3, well under $2/KLUT, including configuration ("Each configuration device costs on average 10 percent of its corresponding Cyclone device") is a compelling value.

At the other end of the spectrum, observe that the two largest announced Cyclone devices offer 2-3X more LUTs and 3-4X more BRAM than the largest shipping Spartan-IIE device, the XC2S300E. Clearly Xilinx must respond to these deficits with new offerings.

As Xilinx and Altera compete with each other to "eat ASICs' lunch", these low-cost FPGA families will also eat into their highly profitable high-end FPGA lines. The last four lines in the above table highlight how the larger Cyclone devices approximately overlap (at least in LUTs) the seven smallest members of the Virtex-II family and the two smallest members of Altera's new Stratix family.

Thursday, September 12, 2002
AT&T Laboratories, Cambridge: JCN: "A low power embedded processor for System-on-Chip design".
"The Xilinx implementation of JCN is compact (1500 Xilinx LUTs, or ~30K ASIC gates) and efficient (25MHz without optimisations on a <$25 FPGA device). It is also technology independent and has comprehensive tool support with a full ANSI C/C++ compiler."
Interesting. Note: in my opinion, 200-300 LUTs is compact. 1500 LUTs is merely average (900 LUTs: MicroBlaze, 1000-1500 LUTs: Nios 2.x).

Murray Disman, ChipCenter: Altera Launches Code:DSP Initiative. "It is effectively positioning NIOS, with its custom instruction capability, as a DSP core."

Brian Dipert, EDN: EDN's Third Annual Programmable-Logic Directory.

Gabe Moretti, EDN: EDA tools bridge the system-on-programmable-chip design gap.

EE Times on reconfigurable computing, and other recent FPGA content
Ron Wilson, EE Times: The constantly shifting promise of reconfigurability. Excellent survey.

"Reconfiguration can happen at design time, deployment time, between execution phases or during execution. Each of these time frames defines a distinct category of reconfigurable systems. ..."

"Experience has shown that when it is possible to compile a logic configuration for particular data sets on the fly, the gains in power and performance can be huge. But implementing such a system requires considerable forethought, a very different approach to system design and a not inconsiderable amount of run-time control software."


Richard Goering, EE Times: Platform-based design: A choice, not a panacea.

'Altera provides a range of operating systems and software development tools. "One thing we're having to do as a hardware company is come to grips with the software guy," Southgate said. "We're delivering tools to software engineers, and we're finding that the lines between hardware and software are getting fuzzy."'
Chris Rowen, Tensilica, in EE Times: Configurability or reconfigurability?.
"... By tailoring a processor core, a system-design team can imbue a processor with more than enough processing capability to handle the processing tasks of some application domain so that the executable algorithms will run in software without any task-specific hardware-acceleration blocks (and often without even assembly-language programming). Although not as open-ended as reconfigurable logic, which allows the complete rewrite of task-specific logic on the fly, the use of tailored microprocessors allows substantial reconfigurability through the more conventional approach of software upgrades. ..."
Kurt Keutzer, U.C. Berkeley, in EE Times: Programmable platforms will rule.
'My colleague, Alberto Sangiovanni-Vincentelli, describes a platform as "a layer of abstraction with two views: The upper view is the abstraction of the design below so that an application could be developed on the abstraction without referring to the lower levels of abstraction. The lower view is the set of rules that integrates components as part of the platform."'

Katherine Compton, NWU, in EE Times: Research focuses on application-specific reconfigurable blocks.

Paul Master, QuickSilver, in EE Times: A look into QuickSilver's ACM architecture.

"The solution is to create a heterogeneous architecture that fully addresses the heterogeneous nature of the algorithms (see figure). Start with five types of nodes: arithmetic, bit manipulation, finite state machine, scala, and configurable input/output used to connect to the outside world."
Greg Ratzel, Cirronet, in EE Times: SoC teams 8-bit core with FPGA. Efficacious application of an Atmel FPSLIC.

Ron Wilson, EE Times: Wide-ranging strategies tackle signal snarls.

"At one extreme -- perhaps the end of the spectrum on which the press concentrates most -- are the high-end horror stories. Third-generation cell-phone handsets, we are told, may require several thousands of Mips of signal-processing horsepower just to capture a signal and wring data packets from it -- a challenge to ponder while palming one of those tiny cell-phone battery packs."
(I wish I could write like that.)

FPGA CPU News, Vol. 3, No. 9
Back issues:
Vol. 3 (2002): Jan Feb Mar Apr May Jun Jul Aug;
Vol. 2 (2001): Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec;
Vol. 1 (2000): Apr Aug Sep Oct Nov Dec.

Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.

Copyright © 2000-2002, Gray Research LLC. All rights reserved.
Last updated: Nov 06 2002