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From: Jan Gray, Gray Research LLC [jan @fpgacpu.org]
Sent: Wednesday, March 15, 2000 12:27 PM
To: fpga-cpu @egroups.com
Subject: Announcement: "Building a RISC System in an FPGA" magazine series, and XSOC/xr16 RISC SoC for XS40

On behalf of Gray Research LLC, I am pleased to announce that the first of three articles in the series "Building a RISC System in an FPGA" is now on newsstands, in the March 2000 (issue #116) of Circuit Cellar magazine. This series shows how to design and implement practical processors and integrated systems-on-a-chip in small FPGAs.

In Part 1, "Tools, Instruction Set, and Datapath", we introduce the XSOC System-on-a-Chip project and the xr16 16-bit pipelined RISC processor core, port the LCC 4.1 retargetable C compiler, write an assembler and simulator, and design and implement the datapath.

In Part 2, "Pipeline and Control Unit Design", we explore the processor pipeline and design its control unit.

In Part 3, "System-on-a-Chip Design", we design and implement the on-chip bus, memory controller, and peripherals including a bilevel VGA display.

The project was designed to be accessible to students and hobbyists. It fits in an Xilinx XC4005XL, targets an XESS XS40 (v1.2 or later) prototyping board, and can be rebuilt with Xilinx Student Edition 1.5.

A beta test of the accompanying XSOC Project on-line materials is now underway. These materials include the documentation, specifications, source code, and schematics needed to build the XSOC Project featured in the magazine articles. (But they don't include the articles themselves.)

If you would like to learn more about XSOC/xr16 and/or participate in the beta test, please visit www.fpgacpu.org/xsoc and follow the instructions. Then let us know how it went -- write to us via the new FPGA CPU / XSOC mailing list, fpga-cpu @egroups.com. Future XSOC announcements will appear there and www.fpgacpu.org.

Thank you,

Jan Gray
President, Gray Research LLC

Copyright © 2000-2002, Gray Research LLC. All rights reserved.
Last updated: Feb 03 2001