FPGA CPU News of March 2001


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Monday, March 26, 2001
Over 200,000 page views to date! Thanks for visiting.

Gaisler Research announces that a fault tolerant version of the open source LEON SPARC core has been fabricated in an Atmel 0.35 micron process. There's a discussion at slashdot.org.

Anthony Cataldo, EE Times: Comms warm a bit to reconfigurable processor. Coming soon, hundreds of Tensilica or ARC Cores per die. Compare to this.

Meanwhile, I've been working a little bit on a faster gr0040 derivative with a simple fetch/execute pipeline organization, but which fits in the same area (under 200 LUTs). Tonight it booted on my Virtex-E proto board for the first time. It's always fun to bring up a new processor.

Sunday, March 18, 2001
Mark Long, E-inSITE (via EDN): Goodbye Processor Cores, Hello FPGAs.

It doesn't have to be an either-or choice. Why not "Hello Processor Cores, Hello FPGAs?"

Part of the problem must be that engineers do not (yet) think of C programmable soft CPU cores as compact, inexpensive, fast solutions.

Not to take anything away from Celoxica or their tools, (the more hardware design innovations, the better), but if a simple embedded processor core is fast enough for the problem, you can replace a ton of custom logic with a 200 logic cell processor and a couple of block RAMs, write it in pure ANSI-C, and ship it yesterday in a <$8 '2S15.

I believe that a family of simple compact soft processor cores (parameterized by performance and area) belong in every practicing FPGA designer's toolbox. In the future you'll sprinkle a couple of them about the design as needed -- e.g. here a dedicated diagnostics interface controller, over here a flash card manager (with FAT filesystem drivers), over there a web browser or web server UI, TCP/IP stack, and MAC processor.

You don't want to do all of that in pure logic gates.

Sure, if there's some computation kernel with performance requirements that merit its own datapath or custom function unit, by all means. Or conversely if the particular computation is more efficiently implemented in a 50 logic cell state machine, skip the processor.

Use the best of both worlds!

Put another way, a hybrid system (which takes some high level language (e.g. C/C++) code and/or some "hardware-design-enhanced" HLL code, optionally profiles it against representative data sets or workloads, and then compiles it so as to seamlessly run some of it on a fixed-or-configurable embedded soft core processor, and some of it in custom gates, state machines, function units, or coprocessors, and/or repeats this compilation process to further optimize the solution) would seem to offer some obvious benefits.

See also Inner loop datapaths.

I just had a wacky way-out idea. Why limit the discussion to executing HLLs? Why not HDLs too? Imagine a clever FPGA synthesis tool which takes Verilog or VHDL source, and synthesizes most of it to gates (LUTs) and flip-flops as usual, but for any low-frequency performance-insensitive HDL, compiles it to C code which is then run in a compact soft CPU core, alongside the synthesized logic in the FPGA. For example, imagine synthesizing the part of a hardware design which defines a bank of slow 115 Kbps UARTs with fancy control features. Maybe they could be replaced by a bit banging software implementation a la Scenix (now Ubicom) style virtual peripherals (see library (PDF)).

Sometimes I'd like to subtitle this weblog blurring the distinction between hardware and software.

Sunday, March 11, 2001
Happy birthday to XSOC/xr16, first described and released last year about this time.

Dave Vanden Bout of XESS has started releasing online chapters of his new Foundation 2.1i Tutorial Book, Pragmatic Logic Design With XILINX Foundation 2.1i.

For years I have recommended Xilinx newbies work through the exercises in Vanden Bout's The Practical XILINX Designer Lab Book, which was bundled with Foundation Student Edition 1.3 and 1.5. It's encouraging to see this new introductory text emerge for use with Student Edition 2.1i.

By the way, I'm not sure whether I'd recommend students and enthusiasts on a strict budget use Student Edition 2.1i (see reviews at amazon.com) or the free Webpack ISE software. While the latter is free, and does apparently support more Virtex and Spartan-II devices, it does not support XC4000 or Spartan devices, and apparently is missing such essential tools as the FPGA Editor.

While I'm on this subject, let me once again plug the Xilinx University Resource Center at Michigan State University, which looks like a great site for educators and students alike.

Now there are at least three families of affordable Xilinx prototyping boards: XESS Corp. XS40, Burch Electronic Designs BED-Spartan2+ and Digilent Digilab XL.

Friday, March 9, 2001
I moved the soc/gr0040 design (paper and slides) presented at DesignCon 2001 to its own project page GR CPUs. I updated the paper to finally include Appendix A which provides the implementation of the 16x16-bit dual ported RAM module ram16x16d.

I also packaged up the extracted Verilog source code with a simple test bench and a demo application.

I also moved various Acrobat-format papers and slides decks to a new subdirectory at Papers. (Sorry if I broke any incoming links.)

Wednesday, March 7, 2001
I updated the Circuit Cellar page with the original drafts of my three part Circuit Cellar article series, Building a RISC CPU and System-on-a-Chip in an FPGA. It's nice to have the whole series in one PDF file, the original (unadulterated) schematics are clearer, and the style is more chatty and conversational.

Sunday, March 4, 2001
The insatiable appetite for smaller, faster, lower energy transistors and wires has the industry scrambling to improve its lithography infrastructure. Steady improvements in optical lithography have carried us through the past four decades of Moore's Law. However, in the very short wavelengths of deep ultraviolet, refractive optics run out of steam.

We'll soon need to change lithography horses to fabricate big chips, in volume, with 50 nm features. This EE Times article reports on recent developments. Then I recommend you take the time to read Keith Diefendorff's fascinating report on EUV LLC's progress to date. "Reflecting the unreflectable" indeed.

David Lammers, EE Times: Rivals vie over next-generation lithography.

Keith Diefendorff, Microprocessor Report: Extreme Lithography: Intel Backs EUV for Next-Generation Lithography:

"But regardless of whether EUVL wins or loses, not enough can be said about the accomplishments of the VNL scientists in just a few years. One by one, technical hurdles that once looked insurmountable have been conquered. Superhuman progress has occurred on many fronts: creating clean high-intensity EUV-light sources; producing ultrahigh-precision optics; taming flare at short wavelengths; producing uniform multilayer mirror coatings; controlling thermal stress in a vacuum environment; mitigating defects on optical elements (including reticles); and designing, manufacturing, and controlling mechanical systems to nanometer accuracy."

Don Sweeney, Science and Technology Review: Extreme Ultraviolet Lithography: Imaging the Future.

Steve Leibson, Microprocessor Report: Analyst's Choice Awards 2001. MPR's Technology of the Year Award: EUV Safeguards Moore's Law for Another Decade.

Friday, March 2, 2001
Michael Santarini, EE Times: Rhines predicts FPGA vendors will rule platform roost.

FPGA CPU News, Vol. 2, No. 3
Back issues: Vol. 2 (2001): Jan Feb; Vol. 1 (2000): Apr Aug Sep Oct Nov Dec.
Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.

Copyright © 2000-2002, Gray Research LLC. All rights reserved.
Last updated: Apr 10 2001