FPGA CPU News of July 2001


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Tuesday, July 31, 2001
We're back and playing catch up.

[06/30/01] Mike Butts has published an independent reimplementation of the xr16 instruction set architecture, written in JHDL (announcement):

"xr16vx is a 16-bit microcontroller design for FPGAs, which I've released as open source programming under the GPL. Including memory, serial and parallel ports and a timer, it fits in only 29% of a Xilinx Spartan-II XC2S100-5, at up to 39 MHz. ..."

"... My xr16vxcpu runs at one cycle per instruction, except taken branches and loads used next cycle. It takes advantage of the dual-ported BlockRAM to fetch instructions and data in parallel. ..."

"Thanks to Jan Gray's XSOC, BYU's JHDL and Xilinx WebPACK ISE, the entire design flow for xr16vx is available on the Web at no cost. ..."

In the Circuit Cellar XSOC articles, I wrote:

"Now let's design an on-chip bus to peripheral interface, to enable robust and easy reuse of peripheral cores, and to help prepare for an ecology of interoperable cores to come."

"It helps to distinguish between core users and core designers. The former will be more numerous, the latter, more experienced. If there are to be ease-of-use tradeoffs, let's make them in favor of core users."

I describe a glue-logic-free on-chip bus, including a versionable abstract control signal bus, whose exact signals and signalling protocols are opaque to (abstracted from) cores users.
"Now a system designer need only instantiate the core, attach CLK, CTRL, D, some SELi, and they're done! ... "How does control signal abstraction help? As long as we revise [XSOC bus building blocks] MEMCTRL and DCTRL together, we can make arbitrary changes to CTRL [signals] without invalidating any existing designs! And to add new bus features, we simply design a new decoder DCTRL_v2, causing no changes to existing DCTRL clients."
Besides its simplicity and ease of use, this design is inexpensive:
"Using DCTRL and our on-chip tri-state bus, the typical overhead per peripheral is just one or two CLBs and perhaps a column of TBUFs."

[07/24/01] Now in the same vein, but in the specific domain of packet transfer interfaces, Altera has announced a new on-chip bus interface, Atlantic.

"With the introduction of the Atlantic standard on-chip interface, designers can bridge different I/O standards simply by wiring Atlantic signals together ..."

"The Atlantic interface is a scalable, high-speed on-chip interface for packet and cell transfer. Optimized for programmable logic devices (PLDs), the Atlantic interface allows designers to quickly and easily join incompatible devices and facilitate the user's IP integration with a simple, clearly defined, and supported interface."

The announcement also has links to the Atlantic Interface Functional Specification. It's simple. I like it. Nice work, Altera.

Murray Disman, ChipCenter: Altera Introduces Interface Standard.

Anthony Cataldo, EE Times: Altera builds on-chip bridge to link interfaces.

'While buses like ARM's Amba are often used for that task, Altera thinks processor-oriented buses consume too much logic resources and introduce latency in FPGAs. "Processor buses have a lot of overhead and they're expensive to implement, especially considering the number of logic elements and memory they need. And they're not well-suited for the data path," said Justin Cowling, a senior manager with Altera's IP division.
I wonder what the minimum cost (in LUTs) of a trivial peripheral (like a byte-wide parallel I/O port) is using AMBA APB and CoreConnect OPB.
'"It's trivial to make adaptations on the fly with FPGAs," said Mike Aaldering, senior developer of IP solutions at Xilinx. "You can take data in and make it wider and lower the clock rate or make it narrower. You've got the flexibility to decide how much logic it will take and what you're going to burn so you don't have to lock yourself into one thing. Nobody's screaming that they've got a problem."'
That's not how you get to a plug-and-play ecology / paradise.

Meanwhile, OpenCores has adopted the WISHBONE SoC interface. See the WISHBONE Project pages. Rudolf Usselmann's OpenCores SoC Bus Review gives a concise overview of CoreConnect, AMBA, and WISHBONE.

And see also SoC On-Chip Buses:

"I can't wait to see an on-chip bus standard (or standards) for FPGAs -- then we might finally see a marketplace of plug-and-play processors and peripherals cores."
One last word. I'm not trying to sell you our bus. (It's not for sale, nor is it saleable, anyway.) I just wish to highlight that in the programmable logic world, an on-chip bus standard need not be a heavyweight artifact that was formerly optimized for an entirely different implementation techology. Well, for better or worse, CoreConnect and AMBA are going to be the shoes that peripheral core designers sport for years to come.

[06/22/01] Therese Poletti, San Jose Mercury News: Rivalry between programmable-chip makers runs deep.

[07/18/01] Xilinx, Altera: Xilinx and Altera Settle Patent Litigation: "... Altera and Xilinx have entered into a royalty-free patent cross license agreement ..." Hmmm.

Peter Clarke, EE Times: Altera will pay Xilinx $20M in peace-making pact.

'"For both companies it helps. There was far too much litigation between us," commented Tom Lavelle, vice president and general counsel for Xilinx. "There are a lot of other companies which could be a threat to us. We need to be protecting Xilinx from other companies than Altera," he said.'
Robert Ristelhueber, EBN: Altera to pay Xilinx $20 million to settle patent feud.

EBN: Altera settles patent infringement case with Lattice.

Peter Clarke, EE Times: HP, Actel back reconfigurable SoC contender.

"But instead of linking a Manhattan array of configurable logic blocks, as in FPGAs, the Elixent array comprises a chess board pattern of 4-bit software-programmable ALUs, together with blocks of embedded RAM. The ALUs cascade flexibly, so that 8-, 16- or 32-bit data can be processed. For an array of 16 ALUs operating at 100 MHz, the theoretical maximum performance is 400 million 16-bit operations per second. ..."

"The compact nature of the configuration data -- 100 bits per 4-bit ALU -- means we can reconfigure in the tens of microseconds, or an order of magnitude less than typical FPGA technology. ..."

See also Elixent. (I would have provided direct links to their press release and to their Technologies frame, but this popup-window and JavaScript-laden site stymied my best efforts to do so.)

Nios uptake
[06/20/01] Altera's Nios Embedded Processor Achieves Widespread Acceptance.

While the competition is still at the development stage, Altera Corporation (Nasdaq: ALTR) has shipped over 1,500 development kits worldwide for its Nios embedded processor solution.
Soon Altera will have shipped more Nios development kits than Gray Research has served up XSOC Kits. :-)

FPGA CPU News, Vol. 2, No. 7
Back issues: Vol. 2 (2001): Jan Feb Mar Apr May Jun; Vol. 1 (2000): Apr Aug Sep Oct Nov Dec.
Opinions expressed herein are those of Jan Gray, President, Gray Research LLC.

Copyright © 2000-2002, Gray Research LLC. All rights reserved.
Last updated: Aug 11 2001