The xr16 CPU Core


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xr16 is a simple 16-bit reduced instruction set computer designed to run integer-only C programs. Its design is optimized for an area-efficient pipelined implementation in a field-programmable gate array and other gate- and interconnect-constrained environments.

The XSOC system-on-a-chip and the xr16 processor core are now provided in both Verilog and Foundation schematics representations.

Some xr16 v1.0 processor core features:

  • a classic pipelined RISC, with 16 16-bit registers and 16-bit instructions;
  • 3 stage pipeline (instruction fetch, decode, execute);
  • approximately 1.4 cycles per instruction in a 0 wait-state memory system;
  • byte addressable memory: load/store bytes and words, with 64 KB addressing;
  • integrated DMA engine: address generator for up to 15 DMA channels;
  • fast interrupt handling: only 6 cycles to take interrupt and return from interrupt;
  • initially targets XC4000E derivatives including Spartan and SpartanXL;
  • resources used: <260 logic cells: (258 4-LUTs, 52 3-LUTs, 165 flip-flops, 112 TBUFs), e.g. less than 25% of an XCS30XL, and (anticipated) less than 2% of an XCV1000;
  • cycle time (in XCS10XL-4) of approx. 25 ns (40 MHz) when sinking and sourcing adjacent test registers, and approx. 40 ns (25 MHz) in the context of a system-on-a-chip addressing on-chip and off-chip resources.
See also The xr16 Specifications (doc\xspecs.pdf) in the XSOC Project distribution.

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Last updated: Feb 03 2001